Programmable logic devices of the types described generally in Spencer U.S. Pat. No. 3,566,153, Birkner et al. U.S. Pat. No. 4,124,899, Hartmann et al. U.S. Pat. No. 4,609,986, Hartmann et al. U.S. Pat. No. 4,617,479 and Hartmann et al. U.S. Pat. No. 4,713,792 can be implemented using fuses, anti-fuses, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) or flash EPROM as their programmable elements. Such devices are typically set up as basically orthogonal arrays of "bit lines" and "word lines" which can be programmably interconnected to achieve a desired logical result. It is known that the programmable interconnections in such devices can be programmed by addressing the appropriate bit lines and word lines, applying the desired programming data, and transferring that data to the interconnection by applying to the selected word lines and bit lines a predetermined programming voltage--e.g., a voltage significantly higher than that encountered in the normal logical operation of the device.
In a programmable device, a programmable array is generally organized as an array of m.times.n programmable elements. In general, to each of the m word lines are connected n EPROM gates, and to each of the n bit lines are connected m EPROM drains.
During programming, any bit at the intersection of a high voltage bit line and a high voltage word line will be programmed. In a conventional programming addressing scheme, in order to reduce the number of selection lines to be interfaced to the array for programming, the address information for the word lines and bit lines is binarily encoded. Thus for a m.times.n array, log.sub.2 m address lines for the word lines and log.sub.2 n address lines for the bit lines, each rounded up to the nearest whole number, are required. The total number of lines to address all interconnections uniquely is the sum of log.sub.2 m rounded up to the nearest whole number and log.sub.2 n rounded to the nearest whole number.
Providing the required number of address input lines presents little difficulty where the programmable logic device is on its own integrated circuit chip. However, for a chip containing several programmable logic devices as well as large numbers of other devices, it would be necessary in a conventional programming scheme to have at least as many programming address lines traced around the chip from programmable device to programmable device as are needed by that device needing the most programming lines. In fact, it might not be possible to use a set of address lines for more than one device, necessitating several times that number of lines. This could present some difficulty on an already densely packed chip. In addition, such chips would require a large number of addressing pins on the package, and additional silicon area to implement the decoders necessary to generate the programming lines going to the word lines and bit lines, in addition to the silicon area required to implement the required number of signal lines.
Also, for integrated circuit chips with multiple arrays of the same or different dimensions, it is necessary to customize the size of each decoder in terms of numbers of input lines and numbers of decoded output lines for each array block. Furthermore, it is generally prudent to physically place each decoder close to its associated array block to avoid to having to route the decoded lines across long distances across the chip. However, areas close to some of the arrays may be needed for other circuit functions during normal operation of the chip. These limitations may present difficulty for the integrated circuit designer in trading off the use of limited silicon area for signal lines and decoders for programming of the programmable elements on the one hand, and implementing other circuits necessary for the performance of intended logic functions during the normal operation of the chip on the other hand.
It would be desirable to be able to provide a way to program a programmable logic device on an integrated circuit chip which occupies a minimum of space on the chip.